FIG. 1 illustrates a conventional graphics processing system 100. Certain conventional components are omitted for the purposes of illustration. A graphics processing unit (GPU) 110 includes a memory controller 112 coupled to dynamic random access memories (DRAMs) 120 via DRAM buses 115. DRAM has specific interface protocols. Thus, GPU 110 requires DRAM memory bus interfaces 125 compatible with DRAM memory.
One drawback of graphics processing system 100 is that the memory bandwidth may be less than desired. The total memory bandwidth scales with the number of DRAM memories 120 that can be simultaneously utilized by GPU 110. The number of DRAMs 110 that can be coupled to GPU 100 is limited by several considerations. One consideration is that the total number of input/output (I/O) interfaces in GPU 100 is limited. For example, in a ball-grid array packaging scheme, there is a limited number of balls per unit area that can be fabricated to provide access to memory. Thus, for a given GPU chip area, a limited number of balls can be allocated to servicing DRAM memory.
Another drawback of graphics processing system 100 is that GPU 110 is required to have DRAM interfaces 125 compatible with different versions of DRAM memory. Double data rate (DDR) memory, for example, has several different protocols, such as DDR and DDR2. Designing GPU 110 to be compatible with different DRAM memory protocols increases the cost and complexity of GPU 110.
Another drawback of graphics processing system 100 relates to the potential patent licensing burden. Many memory protocols are set by standard setting bodies. Such standard setting bodies typically require that participants in the standard setting body license essential patents required to practice the standard on a reasonable and non-discriminatory basis (RAND). Additionally, third parties may also hold patents related to preferred techniques to implement the standard. Thus, designing a GPU 110 to support a number of different memory protocols increases the potential patent licensing burden on GPU 110.
In light of the problems described above, the apparatus, system, and method of the present invention was developed.